Research & Projects

Selected Research Projects

Collaborated on the design of a differential input single output two-stage amplifier (OTA) using current-reuse techniques, achieving a closed-loop gain of ~40dB and a bandwidth of approximately 8 kHz (65nm process).
Conducted comprehensive simulations to analyze the impact of parameters such as width, length, feedback capacitors, and bias current on amplifier performance.
abstract: In implantable neural monitoring, handling increasing data volumes from numerous channels is a challenge for transmission. A viable solution is on-chip data spike detection. This study introduces a low-power circuit integrating an analog front-end, spike enhancement filter, and detector. The amplifier adopts a two-stage operational transconductance design to both perform linear filtering of the biopotential recordings and convert them into current. The spike enhancement filter is designed as a current-mode analog signal processing circuit, utilizing translinear loops to emulate the underdamped dynamics of a particle in a monostable potential well, implemented via a second-order differential equation. The filter's output, enhanced with spikes, undergoes a spike detector stage employing hard thresholding. This circuitry is designed using TSMC 65nm CMOS technology. Through simulations utilizing the Wave_clus database, the proposed system demonstrates an average spike detection sensitivity of 98.99% while consuming 311 nW when powered by a 1 V supply, with a compact footprint of 0.0348 mm2.

A low-power, current-reuse low-noise amplifier (LNA) was developed for MedRadio applications in the 401–406 MHz band, targeting implantable and wearable medical devices. Operating in the subthreshold region at 0.5V, the design achieves over 24 dB gain, a noise figure below 2.1 dB, and IIP3 above –21 dBm, all while consuming under 400 μW.
The LNA features a source-degenerated cascode input stage followed by a noise-canceling second stage. Bulk-bias transistors are used to boost gain, and matching networks are optimized for S11/S22 < –10 dB. A temperature-compensated voltage reference ensures stable operation under threshold voltage (VT) variation.
Layout considerations include off-chip inductors and bondwire modeling to capture realistic parasitics. Post-layout simulations closely match schematic results, demonstrating robust performance and compliance with MedRadio design specifications.

Ultrasonic Distance Sensor
A fully analog ultrasonic time-of-flight system was developed to produce a 0–6V output corresponding to distances from 0 to 60 inches. The design includes a capacitor-based memory for programmable setpoints and triggers a buzzer when the target is too close. The sensor output was also used to control a motorized car, enabling automatic directional response based on proximity.
Laser Tracking Servo
A closed-loop servo system was implemented to align a laser line with the center of a solar cell. Using PWM motor control and proportional feedback, the system enables precise auto-tracking. A gradient-masked solar cell provides accurate position sensing, with additional manual jog controls and laser modulation to enhance noise immunity.
Function Generator
A multi-function waveform generator was designed to output sine, square, triangle, and pulse waveforms with adjustable amplitude, offset, and duty cycle. The circuit achieved clean signal transitions with fast rise and fall times.

Magic Movie.MOV

Designed and implemented a glitch-tolerant monocycle generator in CMOS 65nm technology, creating a clean, single pulse from each rising edge of an input signal while suppressing glitches.
Designed subcomponents, including a delay buffer, SR latch, and output buffer optimized for driving loads up to 10 pF, ensuring reliable pulse generation and glitch filtering.
Conducted schematic, physical layout designs, and post-layout extraction (PEX) to accurately model parasitic effects, achieving precise delay and pulse width control.
Verified functionality through DC and transient simulations, with post-layout testing confirming robustness against input noise and compliance with timing specifications.

Block Diagram of a Glitch-Tolerant Monocycle Generator

Implemented analog comparator layout using matching techniques and common-centroid pattern.
Designed a capacitor DAC (CDAC) using a delta-length capacitor structure to minimize area and unit capacitance.
Led higher-level floorplanning for mega-group and modified TSMC pad ring and seal ring to integrate multiple SAR ADCs.
Validated layout for DRC, LVS, and ERC checks and built proficient skills in debugging warnings and errors.
Performed parasitic extraction (PEX) for resistive and capacitive extraction (RCX) to assess sensitive signal matching.
Focused on matching for better SNR and performance and executed PVT simulations to ensure stability across variations.
Our ADC area: 180um*103um. The chip was taped out in June 2024.

Full Chip Layout

Delta-length capacitor method

Layout of DAC Array

Utilized Matlab to conduct loss analysis aimed at identifying optimal parameter values (such as switch size, capacitor, and inductor values) to achieve high efficiency while minimizing the Figure of Merit (FOM).
Constructed the converter using Cadence and supplied ideal control signals as inputs to evaluate the circuit's viability.
Designed transistor-level sub-blocks: clock generator, dead-time control, error amplifier, comparators, flying capacitor control loop, LDO, gate drivers, level shifters, compensator, phase shifter.
Achieved an efficiency of 85.12%, output voltage ripple of 27.68 mV, and a FOM (power consumption*area) of 0.3180 W/mm² (nominal 1.8V to 0.7V DC to DC converter, but the circuit operates effectively for both D>0.5 and D<0.5).

Utilized gm/Id technique to determine transistor size, realized a 3-op-amp instrumentation amplifier connected to a human body model with a closed-loop gain over 40dB and a bandwidth of around 250Hz, with all transistors operating in the subthreshold region.
Designed a bias circuit and CMFB system to set the body voltage to a value within the input common-mode range of other amplifiers. Added an electrode model and a 60Hz interference model to simulate the closed-loop system, evaluating the common-mode noise and CMRR of the system.
Ran a Monte-Carlo simulation of input-referred noise, gain, power, and CMRR to verify system functionality.
Integrated input referred noise: 1.5751uV, power: 3.48uW, CMRR: 108.5 dB, total capacitance: 951pF.

Page updated

Report abuse